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From Silicon Sample to Volume Order: Design Wins in the Semiconductor Market

31.10.2026
In briefA first silicon sample is not yet revenue — but it is a measurable milestone. Here is why the journey from an early design win to a commercial volume order is so lengthy and risky for semiconductor small caps.
Silicon wafer on a cleanroom inspection table during quality control in a semiconductor laboratory
Illustrative image · AI-generated. Not a depiction of any real company facilities or products.

When 16 Nanometres Makes Headlines — But Not Yet a Business

In the semiconductor industry, nanometres serve as the benchmark for technological progress. When Australian small-cap company Nanoveu (ASX: NVU) announced it had received its first 16-nanometre silicon samples for its ECS chip pipeline, attentive observers responded with interest — and equal caution. Because what sounds like a technical breakthrough is, from a commercial standpoint, only the beginning of a lengthy qualification process.

For investors active in the world of semiconductor small caps, understanding this distinction is critical: between an early process sample and a revenue-generating customer order, there are typically months — sometimes years — as well as a host of technical, regulatory, and commercial hurdles.

Phases from Chip Design to Volume Orders (Months (typical))

Volume orders (after win)up to 24 months
Design win (after qual.)up to 18 months
Qualification cycle6–18 months
First silicon2–4 months
Tape-out to first silicon6–12 months
Schematic reference values based on typical industry development cycles; actual duration varies depending on technology node and customer requirements.

The Semiconductor Development Cycle: From Design to Volume Order

To place the significance of an early design win in context, it helps to examine the typical lifecycle of a new chip. It begins with IP design — the conceptual architecture of the circuit — and progresses through several intermediate stages to mass production. The process can be broadly divided into five phases:

PhaseContentTypical Duration
1. Tape-outFinalisation of the chip layout, handover to the foundry6–12 months
2. First SiliconPhysical samples from the first production run — functional testing follows2–4 months
3. QualificationCustomer validation: yield tests, environmental and lifetime testing6–18 months
4. Design WinOfficial award: customer selects this chip for inclusion in their productMonths after qualification
5. Volume OrdersRevenue-generating deliveries begin — first income received12–24 months after design win

Nanoveu's announcement sits at the transition from Phase 1 to Phase 2 — well before the point at which an order can be considered secured or revenue-relevant. This is not a criticism of the company's achievements, but rather an observation about a structural characteristic of the industry.

Semiconductor qualification laboratory with test rigs for chip certification
Illustrative image · AI-generated. Not a depiction of any real company facilities or products.

Yield, Qualification, and Customer Certification: The Three Bottlenecks

Why does it take so long to move from a silicon sample to a volume order? Three factors are particularly significant:

1. Yield rate: Not every chip produced on a wafer is functional. The so-called yield — the proportion of usable dies — determines the economic viability of the manufacturing process. With a new 16 nm process such as the one Nanoveu is using, initial production runs are typically associated with low yields. Only through iterative process optimisation does the yield rise to commercially viable levels. This process can take many months.

2. Qualification cycles: Before a semiconductor may be used in an end product, it must meet the customer's qualification requirements. Depending on the application area — consumer electronics, automotive, or industrial systems — these requirements vary considerably in their stringency. Automotive suppliers, for example, demand AEC-Q100 certification, which involves its own sequence of tests. Industrial customers apply their own qualification standards.

3. Customer certification: Even once the chip is technically qualified, the customer's overall product — the end device into which the chip is integrated — must itself be certified. This consumes time and resources on the customer's side that the chip supplier has no ability to control.

What Early Milestones Really Mean for Semiconductor Small Caps

Early design wins do carry genuine signal value — they simply need to be interpreted correctly. In the semiconductor industry, a design win is regarded as a strong indicator of future revenues, because chip designs are typically used across multiple product generations by the customer (so-called "sticky revenues"). Once a chip is embedded in a design, it tends to enjoy a degree of recurring demand.

For small-cap companies such as Nanoveu that have yet to generate meaningful revenues, the ability to enter qualification processes with potential customers at all represents real progress. It validates the technical feasibility of the company's own IP and demonstrates that the chosen foundry partnership — the collaboration with the contract semiconductor manufacturer — is functioning.

Investors should, however, keep sight of the gap between signal value and actual value. An analogy from another sector: a pharmaceutical company that initiates a Phase I trial has taken an important step — but regulatory approval remains years away. The position of a first silicon sample in the semiconductor industry is comparable.

Another critical factor is the cash runway: how long does the available capital last to bridge the lengthy path to the first volume revenues? Many semiconductor small caps require additional funding rounds during this phase — which can lead to dilution for existing shareholders. A failed qualification process or the withdrawal of a target customer can also place the company in a difficult position.

Three Key Questions for Assessing Semiconductor Milestone Announcements

Anyone monitoring semiconductor small caps can extract more insight from announcements such as Nanoveu's by asking three structural questions:

First: Where in the development cycle does the company actually stand? First silicon is an earlier milestone than a design win, which in turn comes earlier than a firm customer order (purchase order). These distinctions should be clear when reading press releases.

Second: What is the cash runway? If a company still faces 12 to 18 months of qualification ahead and is incurring monthly operating costs of several hundred thousand dollars, the question arises whether liquidity will last until the first revenues — or whether a capital increase is looming.

Third: How specific and binding is the customer interest? Is there already a qualification agreement in place? A letter of intent? Or is interest in the new chip still informal? The more concrete and binding the customer engagement, the more reliable the milestone is as an indicator of future revenue.

For the broader category of semiconductor small caps, the sector is capital-intensive, technically demanding, and characterised by long development cycles. This makes it an area in which early announcements often generate considerable media interest — and in which the gap between an announcement and actual revenues is frequently underestimated.

What the Silicon Sample Moment Shows — and What It Does Not

First silicon samples from a 16 nm process represent a genuine milestone for a small company such as Nanoveu (ASX: NVU): they demonstrate that the chip architecture has successfully been translated into silicon and that the collaboration with the foundry is working. This is technically significant and by no means a given for a company of this size.

What the milestone does not show: it says nothing yet about whether yield rates are economically viable, whether customer qualifications will be completed successfully, whether the company is funded through to its first volume revenues, or whether customer demand will materialise at the expected scale. All of these remain open questions that must be answered over the coming 12 to 24 months.

The gap between signal value and fundamental value is rarely as pronounced in the semiconductor industry as it is at this early stage. Investors who learn to read this distinction are better positioned to assess announcements objectively — regardless of how small the nanometre figure in the headline may be.

Key Terms at a Glance

Design Win
An official award from a customer selecting a specific chip for inclusion in their product. A design win is not a firm order, but signals a strong intention to use the chip — typically months before the first volume order.
First Silicon
The first physical chip samples produced from a new manufacturing process. They serve for technical validation but are still far from production readiness.
Yield Rate
The proportion of functional chips relative to the total number of dies produced on a wafer. Low yield rates significantly increase production costs and are typical in early process runs.
Qualification Cycle
The testing process a chip must complete before a customer may use it in their end product. Duration: typically 6 to 18 months, depending on the application (consumer, automotive, industrial).
Foundry
A specialised semiconductor manufacturer (e.g. TSMC, GlobalFoundries) that produces chip designs from other companies on a contract basis. Small-cap chip developers such as Nanoveu are typically so-called fabless companies — they do not own their own manufacturing facility.
Cash Runway
The period for which a company has sufficient liquidity at its current rate of expenditure (burn rate). In the semiconductor sector, a long cash runway is critical, as development cycles can span two to four years.
Dilution
The reduction in value of existing shareholdings resulting from the issuance of new shares as part of a capital increase. In capital-intensive sectors such as semiconductors, dilution is a frequent risk for shareholders of pre-revenue small caps.
Tape-out
The moment at which the completed chip layout is handed over to the foundry for production. Depending on the technology node, a tape-out can cost hundreds of thousands to millions of US dollars — and is therefore often a critical liquidity event for small companies.

⚠️ Important notice: This article is for informational and educational purposes only. It does not constitute investment advice, a recommendation, or a solicitation to buy or sell any security. Investments in small-cap exploration and mining companies carry a high risk, including the potential total loss of capital. Before making any investment decision, consult a registered financial advisor and conduct your own analysis. Aktienatlas-Redaktion is not responsible for decisions taken based on the content published here.

Educational content only, not investment advice. Small caps are highly speculative and total loss is possible.